1. Field of Invention
The present invention generally relates to semiconductor processing. More particularly, the present invention relates to forming trench isolation structures during semiconductor device fabrication.
2. Discussion of the Related Art
With the ever-increasing number of semiconductor devices being built on a single chip, the art of isolating semiconductor devices has become an important aspect of modern semiconductor and integrated circuit technology. Improper isolation among devices will cause current leakage, which can consume a significant amount of power. Improper isolation can also result in defects such as noise margin degradation, voltage shift, and crosstalk.
Trench isolation is an isolation technique developed especially for a semiconductor chip with high integration. Shallow trench isolation (STI), in particular, is often used in the fabrication of integrated circuit devices to isolate active areas from one another. The trench regions are formed in the semiconductor substrate by recessing the substrate deep enough for isolation and filling with insulating material to provide the isolation among active devices or different well regions.
High density plasma chemical vapor deposition (HDP-CVD) of dielectric material has been previously used for STI gapfill. The HDP-CVD process includes a deposition component and a sputtering component to simultaneously deposit and etch the dielectric material in the same reaction, thereby allowing material to be deposited very densely and without voids.
Liner oxide layers have been used to prevent plasma damage to an underlying substrate from the HDP-CVD gapfill process. Such a method requires that the liner oxide layer be of sufficient thickness to prevent damage to underlying layers from the sputtering component of the HDP-CVD process. For example, the use of one layer of thick thermal oxide is known, but such a technique has caused corner effects such as gate wrap around and parasitic leakage. Furthermore, in the fabrication of flash memory devices, the use of only a single layer of thick thermal oxide will cause the tunnel oxide to be thicker at the edges of the active area.
The use of a thermal oxide layer in conjunction with a high temperature CVD oxide (HTO) is known to advantageously solve the aforementioned problems. However, this technique may cause grooving of the oxide in a subsequent etch step, as shown in FIG. 1. Oxide layers 2 and 4 form grooves 8 while bulk oxide layer 6 is substantially level along a top surface of the dielectric layers. Furthermore, such a technique requires three steps of oxide deposition: one thermal oxide layer formation; one HTO layer formation; and one gapfill oxide layer formation. Thus, such a process involves a relatively high thermal budget and long process time.
Therefore, what is needed is a trench isolation technique that protects the underlying layers and/or the substrate from plasma damage and also provides a flat and uniform surface level of the dielectric in the trench after an etch. Furthermore, a highly efficient trench isolation process in terms of process cycle time and thermal budget is desirable.